1. Field of the Invention
The present invention relates to a Double Data Rate DRAM (DDR DRAM) based electronic computer memory system, and more specifically to upgrading the data transfer rate in a DRAM.
2. Background Art
The main memory of a computer stores the data and program required by a central processing unit for executing instructions for a given task. The time required to access data stored in the main memory detracts from the time available to execute instructions, and slows down the overall opening speed of the computer. Anything that reduces the time for memory access serves to increase the operating speed of the computer. The main memory is stored in semiconductor memory devices called Random Access Memory (RAM) devices. The two most common types of RAM are DRAM or Dynamic Random Access Memory and SRAM or Static Random Access Memory. Each device has its advantages and its disadvantages.
Network processors are becoming more important in the computer world for their ability to forward, route, and filter frames comprising defined length sequences of bits of information. As bigger networks are built, the network processor needs the ability to service more and more traffic and the bandwidth requirements continue to increase. In order to build a network processor that can handle several gigabit ports, previous designs relied on SRAM for data storage in order to keep up with the high bandwidth requirements to transmit large quantities of data per unit of time. However, SRAM drove up the costs of those solutions, and cheaper solutions were pursued. DRAM has the advantages of lower costs and larger array sizes which would help with the larger data stores needed by the network processors. There are several disadvantages associated with the use of DRAM chips. One is their high latency during xe2x80x98readxe2x80x99 or xe2x80x98writexe2x80x99 access (several cycles delay in order to address the DRAM). Another disadvantage is the complex rules concerning reading and writing the memory. RAS and CAS rules limit random access to the memory unlike the access that is possible with SRAMs. There is also the need to periodically refresh the memory every 2 ms or so due to the inherent capacitor leakage.
The newer Double Data Rate DRAMs (DDR DRAs) allow data to be transferred twice as fast as regular DRAMs by moving the data on both the rising and falling clock edge. Using this approach, data transferred on the rising edge and the falling edge of the clock, effectively doubles the bandwidth. These DDRs have speeds up to 133 MHz (and going higher) which allow up to 4.2 Gbit of raw bandwidth.
Using fixed sized buffers works well for network systems like ATMs which have fixed packet sizes. However, for networks like Ethernet, which have variable frame sizes, using the 64 byte buffers can cause a significant performance hit on the data store. For example, assume a 68 byte frame is stored in the data store. This would require 2 buffers to store the data, 2 xe2x80x98writexe2x80x99 windows to xe2x80x98writexe2x80x99 the data to DRAM, and 2 xe2x80x98readxe2x80x99 windows to read the data from DRAM. For purposes of describing the present invention, xe2x80x98windowxe2x80x99 is defined as a time slot during which a read or write operation is being performed to or from the DRAM. The system bandwidth is cut almost in half in order to op this 68 byte frame. Since the DRAM has complex rules concerning RAS and CAS and does not support completely random access, the DRAM bandwidth would be lost when accessing the 68 byte frame if something was not done to compensate for this situation.
One objective of the present invention is the use of a DRAM system to provide increased storage and data transfer rates for network processors.
Another objective is to achieve wider bandwidth transfer of data for use by network processors,
Still another objective is the control of the movement of data needed by the network processor to maximize the number of clock cycles used for data transfer to and from a DRAM.
Yet another objective is to have the capability of arbitrating the service of multiple frames by the network processor.
Finally, it is an objective to be able to randomize DRAM xe2x80x98readxe2x80x99 and xe2x80x98writexe2x80x99 access.
These and other objectives that will become self evident to one skilled in the art upon reading and understanding this description are achieved in the following manner.
An improved data transfer system for a network processor uses a dynamic random access memory chip (DRAM) including one or more of the following features: a) A pair of Double Data Rate DRAMS in parallel, each capable of moving data on each edge of a time clock; b) A Time-Division-Multiplexer to allow 4 banks of data to be read by the network processor followed by 4 data banks to be written during each time cell, and c) Valid Bank Vectors useful with varying size data frames to increase overall bandwidth of the DRAM dependent on the length of the frame.
More particularly, the invention relates to an improved data transfer system for a plurality of network processors using a dynamic random access memory (DRAM) storage. The system includes a pair of Double Data Rate DRAM chips in parallel, each capable of moving data on both the rising and falling edges of a time clock. It also includes a multiplexer to allow 4 memory banks of data to be read by each network processor followed by 4 memory banks to be xe2x80x98writtenxe2x80x99 by each network processor during one 20 cycle cell of the time clock. The system further includes a serial bus and pipelines for the transfer of the xe2x80x98readxe2x80x99 data and the xe2x80x98writexe2x80x99 data between the DDR DRAMS and the respective network processor. Preferably, it utilizes a plurality of fixed size data store buffers, with each buffer having a 64 byte capacity. Each memory bank comprises xc2xc of the data store. The system can also include a priority program that allows random access for xe2x80x98readxe2x80x99 and xe2x80x98writexe2x80x99 to the DDR DRAM.
In another aspect of the invention, a method is described for storing and moving data for use by a network processor. The method includes the steps of: a) storing the data in first and second DDR DRAM chips working in tandem and having synchronized clocks; b) establishing a data movement pattern comprising a predetermined number of cycles in each repeating cell of the DDR DRAM clocks; c) dedicating a contiguous group of cycles in the pattern to full xe2x80x98readxe2x80x99 during a xe2x80x98readxe2x80x99 window; and d) dedicating a second contiguous group of cycles in the pattern to full xe2x80x98writexe2x80x99 during a xe2x80x98writexe2x80x99 window. The method may include the additional step of storing data from each read window or from each write window into one of a plurality of buffers. Each window preferably comprises a burst of 64 bytes of data and each buffer has a store capacity of 64 bytes. The data is pipelined to allow 4 banks to be read during the xe2x80x98readxe2x80x99 window, followed by 4 be to be written during the xe2x80x98writexe2x80x99 window. Each bank preferably comprises xc2xc of the of the data store. The data is read or is written in bursts of 64 bytes.
The invention flier comprises an arbitration system for a network processor and the method for providing a high bandwidth data movement for multiple frames being serviced by the network processor. The system comprises establishing time slots or windows for reading each of the four banks (labeled a, b, c, and d) in the DRAM chip and time slots for writing each of the four banks. The system then determines which of the banks needs to be read and which of the banks need to be written for a given five. It accesses the bank during the appropriate read or write time slots that are required by said given frame. It then reviews all frames needing xe2x80x98readxe2x80x99 access during a given period of time and arbitrates for all xe2x80x98axe2x80x99 banks between all frames needing xe2x80x98readxe2x80x99 access to the xe2x80x98axe2x80x99 bank. In similar fashion, it arbitrates for all xe2x80x98bxe2x80x99, xe2x80x98cxe2x80x99, and xe2x80x98dxe2x80x99 banks for a frame requiring access to the other banks. Then, it repeats the steps of reviewing the frames and arbitration for all other flumes needing xe2x80x98writexe2x80x99 access.
Finally, the invention includes a method of providing a network sensor with random xe2x80x98readxe2x80x99 and xe2x80x98writexe2x80x99 access to a DRAM. This method comprises the steps of; sequencing the xe2x80x98readxe2x80x99 and xe2x80x98writexe2x80x99 access to a plurality of banks a, b, c, and d of a DRAM chip. During the xe2x80x98readxe2x80x99 step, arbitration is used to give priority to bank xe2x80x98axe2x80x99 for any read commands that need to be fulfilled. If no xe2x80x98readxe2x80x99 access is available in bank xe2x80x98axe2x80x99 the bank is given access to a xe2x80x98writexe2x80x99 command and bank xe2x80x98bxe2x80x99 is then given a xe2x80x98writexe2x80x99 command as well. If the access to bank xe2x80x98bxe2x80x99 is different than the access to bank xe2x80x98axe2x80x99, bank xe2x80x98bxe2x80x99 is bypassed in favor of bank xe2x80x98cxe2x80x99 since there is not a sufficient time delay between the two adjacent banks to switch between xe2x80x98readxe2x80x99 and xe2x80x98writexe2x80x99. When the system skips to bank c, it modifies the arbitration to give priority to bank xe2x80x98cxe2x80x99 whether it is read or write. By then sufficient time will have elapsed to allow the system to switch from xe2x80x98readxe2x80x99 to xe2x80x98writexe2x80x99. In this manner, the system can accommodate the data exchange through this bank whether it is xe2x80x98readxe2x80x99 or xe2x80x98writexe2x80x99. These steps are repeated during a xe2x80x98writexe2x80x99 window. This technique of random access is particularly useful for processing control information.